In system-on-a-chip (SOC) applications clock distribution is utilized to spread the high-speed clock from the clock generator circuit to the various functional blocks of the SOC. In addition to high power consumption there are additional problems with conventional clock distribution schemes including:                1. Duty cycle error (DCE) amplification;        2. Quadrature phase error (IQE) accumulation; and        3. Clock signal jitter accumulation including of supply induced jitter and device noise induced jitter.        
To reduce duty cycle error and quadrature phase error problems a lower clock signal fan-out may be used at the cost of more stages, more power consumption, and more clock signal jitter.
A conventional clock distribution circuit 100 is illustrated in FIG. 1. To minimize signal propagation delay a clock signal fan-out number of four (FO4) may be utilized. Cross-coupled inverter pairs 102 are utilized along the clock distribution circuit to maintain the differential nature of the clocks. As the clock frequency increases the bandwidth of the FO4 clock distribution scheme with cross-coupled inverter pairs becomes insufficient leading to increased duty cycle error or even missing clock edges (clock failure) at the circuits driven by the clock. To maintain bandwidth the fan-out number may be reduced and the number of clock distribution stages increased resulting in higher power consumption, increased clock signal propagation delay, and higher clock signal jitter.